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august 2010 doc id 14497 rev 4 1/19 19 l6393 half-bridge gate driver features high voltage rail up to 600 v dv/dt immunity 50 v/nsec in full temperature range driver current capability: ? 290 ma source, ? 430 ma sink switching times 75/35 nsec rise/fall with 1 nf load 3.3 v, 5 v cmos/ttl inputs comparators with hysteresis integrated bootstrap diode uncommitted comparator adjustable dead-time compact and simplified layout bill of material reduction flexible, easy and fast design application motor driver for home appliances factory automation industrial drives and fans hid ballasts power supply units description the l6393 is a high-voltage device manufactured with the bcd ?off-line? tech nology. it is a single chip half-bridge gate driver for n-channel power mosfet or igbt. the high side (floating) section is designed to stand a voltage rail up to 600 v. the logic inputs are cmos /ttl compatible down to 3.3 v for easy interfacing microcontroller/dsp. the ic embeds an uncommitted comparator available for protections against overcurrent, overtemperature, etc. 3/ 3/ $)0 $)0 table 1. device summary order codes package packaging l6393n dip-14 tu b e l6393d so-14 l6393dtr tape and reel www.st.com
contents l6393 2/19 doc id 14497 rev 4 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 ac operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 dc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 waveforms definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1 cboot selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
l6393 block diagram doc id 14497 rev 4 3/19 1 block diagram figure 1. block diagram 6 ## 56 $%4%#4)/. ,%6%, 3( ) &4%2 "//4342!0 $2)6%2 3 6 ## ,6' $2)6%2 (6' $2)6%2 56 $%4%#4)/. 2 &,/!4).'3425#452% from,6' ,/')# 3( //4 4(2/5'( 02%6%. 4) /. #/- 0!2!4/2 $%!$ 4)-% 6 "//4 (6' 0(!3% /54 "2!+% ,6' 3$ #0/54 #0 #0 $4 '.$ ".w
pin connection l6393 4/19 doc id 14497 rev 4 2 pin connection figure 2. pin connection (top view) table 2. pin description pin n# pin name type function 1 phase i driver logic input (active high) 2 sd (1) 1. the circuit provides less than 1 v on the lvg and hv g pins (@ isink = 10 ma), with vcc > 3 v. this allows omitting the ?bleeder? resistor connected bet ween the gate and the source of the external mosfet normally used to hold the pin low; the gate driv er assures low impedance also in sd condition. i shut down input (active low) 3 brake i driver logic input (active low) 4 vcc p lower section supply voltage 5 dt i dead time setting 6 cpout o comparator output (open drain) 7 gnd p ground 8 cp- i comparator negative input 9 cp+ i comparator positive input 10 lvg (1) o low side driver output 11 nc not connected 12 out p high side (floating) common voltage 13 hvg (1) o high side driver output 14 boot p bootstrapped supply voltage !-v 0(!3% "//4 3$ (6' "2!+% /54 6## . # $4 ,6' #0 #0/54 #0 '.$
l6393 truth table doc id 14497 rev 4 5/19 3 truth table note: x: don?t care in the l6393 ic the two input signals phase and brake are fed into an and logic port and the resulting signal is in phase with the high side output hvg and in opposition of phase with the low side output lvg. this means that if brake is kept to high level, the phase signal drives the half-bridge in phase with the hvg output and in opposition of phase with the lvg output. if brake is set to low level the low side output lvg is always on and the high side output hvg is always off, whatever the phase si gnal. this kind of lo gic interface provides the possibility to control the power stages using the phase si gnal to select the current direction in the bridge and the brake signal to perform current slow decay on the low sides. from the point of view of the logic operations the two signals phase and brake are completely equivalent, that means the two signals can be exchanged without any change in the behavior on the resulting output signals (see the figure 1 on page 3 ). note: the dead time between the turn off of one power switch and the turn on of the other power switch is defined by the resistor connected between dt pin and the ground. table 3. truth table inputs outputs sd phase brake lvg hvg l x x l l h l l h l h l h h l h h l h l h h h l h
electrical data l6393 6/19 doc id 14497 rev 4 4 electrical data 4.1 absolute maximum ratings note: esd immunity for pins 12, 13 and 14 is guaranteed up to 1 kv (human body model) 4.2 thermal data table 4. absolute maximum ratings symbol parameter value unit min max v cc supply voltage -0.3 21 v v out output voltage v boot - 21 v boot + 0.3 v v boot bootstrap voltage -0.3 620 v v hvg high side gate output voltage v out - 0.3 v boot + 0.3 v v lvg low side gate output voltage -0.3 v cc + 0.3 v v cp+ comparator positive input voltage -0.3 v cc + 0.3 v v cp- comparator negative input voltage -0.3 v cc + 0.3 v v i logic input voltage -0.3 15 v v od open drain voltage -0.3 15 v dv out /dt allowed output slew rate 50 v/ns p tot total power dissipation (t a = 25 c) 800 mw t j junction temperature 150 c t stg storage temperature -50 150 c table 5. thermal data symbol parameter so-14 dip-14 unit r th(ja) thermal resistance junction to ambient max. 165 100 c/w
l6393 electrical data doc id 14497 rev 4 7/19 4.3 recommended operating conditions table 6. recommended operating conditions symbol pin parameter test condition min max unit v cc 4 supply voltage 10 20 v v bo (1) 1. v bo = v boot - v out 14-12 floating supply voltage 9.8 20 v v out 12 dc output voltage - 9 (2) 2. lvg off. v cc = 10 v. logic is operational if v boot > 5 v, refer to an2785 for more details. 580 v v cp- 8 comparator negative input voltage v cp+ 2.5v v cc (3) 3. at least one of the comparator's input must be lower than 2.5v to guarantee proper operation. v v cp+ 9 comparator positive input voltage v cp- 2.5v v cc (3) v f sw switching frequency hvg, lvg load c l = 1 nf 800 khz t j junction temperature -40 125 c
electrical characteristics l6393 8/19 doc id 14497 rev 4 5 electrical characteristics 5.1 ac operation v cc = 15 v, t j = +25 c table 7. ac operation electrical characteristics symbol pin parameter test condition min typ max unit ac operation t on 1,3 vs 10, 13 high/low side driver turn-on propagation delay v out = 0 v v boot = v cc c l = 1 nf v i = 0 to 3.3 v see figure 3 on page 9 50 125 200 ns t off high/low side driver turnoff propagation delay 50 125 200 ns t sd 2 vs 10, 13 shut down to high/low side propagation delay 50 125 200 ns mt delay matching, hs and ls turn-on/off 30 ns dt 5 dead time setting range (1) r dt = 0, c l = 1 nf 0.1 0.18 0.25 s r dt = 37 k ? , c l = 1 nf, c dt = 100 nf 0.48 0.6 0.72 r dt = 136 k ? , c l = 1 nf, c dt = 100 nf 1.35 1.6 1.85 r dt = 260 k ? , c l = 1 nf, c dt = 100 nf 2.6 3.0 3.4 mdt matching dead time (2) r dt = 0 ? ; c l = 1 nf 80 ns r dt = 37 k ? ; c l = 1 nf; c dt = 100 nf 120 r dt = 136 k ? ; c l = 1 nf; c dt = 100 nf 250 r dt = 260 k ? ; c l = 1 nf; c dt = 100 nf 400 t r 10, 13 rise time c l = 1 nf 75 120 ns t f fall time c l = 1 nf 35 70 ns 1. see figure 4 on page 9 2. mdt = i dt lh - dt hl i see figure 5 on page 12
l6393 electrical characteristics doc id 14497 rev 4 9/19 figure 3. timing figure 4. typical dead time vs. dt resistor value lvg lvg/hvg hvg 50% 10% 90% 50% t r t f t on t off 90% 10% sd 90% 50% t f t sd 10% 50% 10% 90% 50% t r t f t on t off 90% 10% phase brake in phase brake in 0 0.5 1 1.5 2 2.5 3 3.5 0 50 100 150 200 250 300 rdt (kohm) dt (us) approximated formula for rdt calculation (typ.): rdt[k] = 92.2 dt[s] - 16.6
electrical characteristics l6393 10/19 doc id 14497 rev 4 5.2 dc operation v cc = 15 v; t j = +25 c table 8. dc operation electrical characteristics symbol pin parameter test condition min typ max unit low supply voltage section v cc_hys 4 v cc uv hysteresis 1.2 1.5 1.8 v v cc_thon v cc uv turn on threshold 9 9.5 10 v v cc_thoff v cc uv turn off threshold 7.6 8 8.4 i qccu undervoltage quiescent supply current v cc = 7 v; sd = 5 v; phase and brake = gnd; r dt = 0 ; cp + = gnd; cp - = 0.5 v 110 150 a i qcc quiescent current v cc = 15 v; sd = 5 v; phase and brake = gnd; r dt = 0 ; cp + = gnd; cp - = 0.5 v 600 1000 bootstrapped supply voltage section (1) v bo_hys 14 v bo uv hysteresis 0.8 1.0 1.2 v v bo_thon v bo uv turn on threshold 8.2 9 9.8 v v bo_thoff v bo uv turn off threshold 7.3 8 8.7 v i qbou undervoltage v boot quiescent current v bo = 7 v sd = 5 v; phase and brake = 5 v; r dt = 0 ; cp + = gnd; cp - = 0.5 v 40 100 a i qbo v boot quiescent current v bo = 15 v sd = 5 v; phase and brake = 5 v; r dt = 0 ; cp + = gnd; cp - = 0.5 v 140 210 i lk high voltage leakage current v hvg = v out = v boot = 600 v 10 r dson bootstrap driver on resistance (2) lvg on 120 driving buffers section i so 10, 13 high/low side source short circuit current v in = v ih (t p < 10 s) 200 290 ma i si high/low side sink shor t circuit current v in = v il (t p < 10 s) 250 430 ma logic inputs v il 1, 2, 3 low logic level voltage 0.8 v v ih high logic level voltage 2.25 v
l6393 electrical characteristics doc id 14497 rev 4 11/19 symbol pin parameter test condition min typ max unit i phaseh 1 phase logic ?1? input bias current phase = 15 v 20 40 100 a i phasel phase logic ?0? input bias current phase = 0 v 1 i brakeh 3 brake logic ?1? input bias current brake = 15 v 20 40 100 i brakel brake logic ?0? input bias current brake = 0 v 1 i sdh 2 sd logic ?1? input bias current sd = 15 v 10 30 100 i sdl sd logic ?0? input bias current sd = 0 v 1 1. v bo = v boot - v out 2. r dson is tested in the following way: r dson = [(v cc - v cboot1 ) - (v cc - v cboot2 )] / [i 1 (v cc ,v cboot1 ) - i 2 (v cc ,v cboot2 )] where i 1 is pin 14 current when v cboot = v cboot1 , i 2 when v cboot = v cboot2. table 8. dc operation electrical characteristics (continued) table 9. sense comparator symbol pin parameter test conditions min typ max unit v io 8, 9 input offset voltage -15 15 mv i ib input bias current v cp+ = 1 v 1 a v ol 6 open drain low level output voltage i od = - 3 ma 0.5 v t d_comp comparator delay r pu = 100 k to 5 v; v cp- = 0.5 v 90 130 ns sr 6 slew rate c l = 180 pf, r pu = 5 k 60 v/s
waveforms definition l6393 12/19 doc id 14497 rev 4 6 waveforms definition figure 5. dead time waveform definition lvg hvg phase brake dt lh dt hl dt hl dt lh
l6393 typical application diagram doc id 14497 rev 4 13/19 7 typical application diagram figure 6. application diagram !-v 89 '(7(&7,21 /(9(/ 6+ , )7(5 %227675$3'5,9(5 6 9 && /9* '5,9(5 9 && +9* '5,9(5 +9* +9 72/2$' 287 /9* %227 &e r r w 89 '(7(&7,21 *1' &3287 5 /2*,& 6+ 227 7+528*+ 35(9(17,21 )/2$7,1*6758&785( &203$5$725 &3 9 &3 6' '7 '($' 7,0( iurp/9* %5$.( 3+$6(
bootstrap driver l6393 14/19 doc id 14497 rev 4 8 bootstrap driver a bootstrap circuitry is needed to supply the hi gh voltage section. this function is normally accomplished by a high voltage fast recovery diode ( figure 7 .a). in the l6393 a patented integrated structure replaces the external diode. it is realized by a high voltage dmos, driven synchronously with the low side driver (lvg), with diode in series, as shown in figure 7 .b. an internal charge pump ( figure 7 .b) provides the dmos driving voltage. 8.1 c boot selection and charging to choose the proper c boot value the external mos can be seen as an equivalent capacitor. this capacitor c ext is related to the mos total gate charge: the ratio between the capacitors c ext and c boot is proportional to the cyclical voltage loss. it has to be: e.g.: if q gate is 30 nc and v gate is 10 v, c ext is 3 nf. with c boot = 100 nf the drop would be 300 mv. if hvg has to be supplied for a long time, the c boot selection has to take into account also the leakage and quiescent losses. e.g.: hvg steady state consumption is lower than 200 a, so if hvg t on is 5 ms, c boot has to supply 1 c to c ext . this charge on a 1 f capacitor means a voltage drop of 1 v. the internal bootstrap driver gives a great advantage: the external fast recovery diode can be avoided (it usually has great leakage current). this structure can work only if v out is close to gnd (or lower) and in the meanwhile the lvg is on. the charging time (t charge ) of the c boot is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. the bootstrap driver introduces a voltage drop due to the dmos r dson (typical value: 120 ). at low frequency this drop can be neglected. anyway increasing the frequency it must be taken in to account. c ext q gate v gate -------------- - = c boot c ext ?
l6393 bootstrap driver doc id 14497 rev 4 15/19 the following equation is useful to compute the drop on the bootstrap dmos: where q gate is the gate charge of the external power mos, r dson is the on resistance of the bootstrap dmos, and t charge is the charging time of the bootstrap capacitor. for example: using a power mos with a total gate charge of 30 nc the drop on the bootstrap dmos is about 1 v, if the t charge is 5 s. in fact: v drop has to be taken into account when the voltage drop on c boot is calculated: if this drop is too high, or the circuit topology doesn?t allo w a sufficient charging time, an external diode can be used. figure 7. bootstrap driver v drop i ch e arg r dson v drop q gate t ch e arg ------------------- r dson = = v drop 30nc 5 s -------------- - 120 0.7v ? = !-v 4/,/!$ (6 (6' a b ,6' (6' ,6' # "//4 4/,/! $ (6 # "//4 $ "//4 "//4 6 3 6 3 6 /54 "//4 6 /54
package mechanical data l6393 16/19 doc id 14497 rev 4 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark. figure 8. package dimensions table 10. dip-14 mechanical data dim. mm. inch min typ max min typ max a1 0.51 0.020 b 1.39 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 2.54 0.050 0.100
l6393 package mechanical data doc id 14497 rev 4 17/19 figure 9. package dimensions table 11. so-14 mechanical data dim. mm. inch min typ max min typ max a 1.75 0.068 a1 0.1 0.2 0.003 0.007 a2 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.019 c1 45 (typ.) d 8.55 8.75 0.336 0.344 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 f 3.8 4.0 0.149 0.157 g 4.6 5.3 0.181 0.208 l 0.5 1.27 0.019 0.050 m 0.68 0.026 s 8 (max.)
revision history l6393 18/19 doc id 14497 rev 4 10 revision history table 12. document revision history date revision changes 03-mar-2008 1 initial release 18-mar-2008 2 cover page updated 17-nov-2009 3 updated: cover page, table 4 on page 6 , table 6 on page 7 , ta bl e 7 on page 8 , table 8 on page 10 , table 9 on page 11 11-aug-2010 4 updated: table 1 on page 1, table 6 on page 7 and table 8 on page 10
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